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ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 5 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
16 years 3 days ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
DAC
2006
ACM
16 years 3 days ago
Hierarchical power distribution and power management scheme for a single chip mobile processor
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method ...
Toshihiro Hattori, Takahiro Irita, Masayuki Ito, E...
ICC
2000
IEEE
123views Communications» more  ICC 2000»
15 years 10 months ago
Design of Adaptive Bit Interleaved TCM for Rayleigh Fading Channels
fixed rate coding in terms of SNR and average throughput was obtained. In fact, the concept of variable rate adaptive In this paper, we propose a bandwidth efficient error cor- cod...
Vincent K. N. Lau
MOBIHOC
2000
ACM
15 years 10 months ago
Low power rendezvous in embedded wireless networks
ln the future, wireless networking will be embedded into a wide variety of common, everyday objects [1]. In many embedded networking situations, the communicating nodes will be ver...
Terry Todd, Frazer Bennett, Alan Jones