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CF
2009
ACM
16 years 1 months ago
Core monitors: monitoring performance in multicore processors
As we reach the limits of single-core computing, we are promised more and more cores in our systems. Modern architectures include many performance counters per core, but few or no...
Paul E. West, Yuval Peress, Gary S. Tyson, Sally A...
CGO
2004
IEEE
15 years 10 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
16 years 7 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
HPCA
2005
IEEE
16 years 7 months ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
ICWS
2009
IEEE
16 years 4 months ago
Scalable and Reliable Location Services through Decentralized Replication
—One of the critical challenges for service oriented computing systems is the capability to guarantee scalable and reliable service provision. This paper presents Reliable GeoGri...
Gong Zhang, Ling Liu, Sangeetha Seshadri, Bhuvan B...