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VLSID
2005
IEEE
139views VLSI» more  VLSID 2005»
16 years 7 months ago
Variable Input Delay CMOS Logic for Low Power Design
Modern digital circuits consist of logic gates implemented in the complementary metal oxide semiconductor (CMOS) technology. The time taken for a logic gate output to change after...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
IEEESCC
2005
IEEE
16 years 5 days ago
Web Services Composition: A Story of Models, Automata, and Logics
eal world”, represented abstractly using (time-varying) first-order logic predicates and terms. A representative composition result [11] here uses a translation into Petri nets. ...
Richard Hull
DOLAP
2006
ACM
16 years 17 days ago
Towards a logical multidimensional model for spatial data warehousing and OLAP
Decision support systems (DSS) may be enhanced qualitatively if they are able to also deal with spatial dimensions and measures. Regardless the evident importance of using data wa...
Marcus Costa Sampaio, Andre Gomes de Sousa, Cl&aac...
PACS
2004
Springer
115views Hardware» more  PACS 2004»
15 years 12 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...
FPGA
1997
ACM
118views FPGA» more  FPGA 1997»
15 years 10 months ago
Module Generation of Complex Macros for Logic-Emulation Applications
Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design veri cation. Using an emulator, designers can realize designs through a soft...
Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen