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BMCBI
2006
195views more  BMCBI 2006»
15 years 6 months ago
CAFTAN: a tool for fast mapping, and quality assessment of cDNAs
Background: The German cDNA Consortium has been cloning full length cDNAs and continued with their exploitation in protein localization experiments and cellular assays. However, t...
Coral del Val, Vladimir Yurjevich Kuryshev, Karl-H...
PDP
2010
IEEE
16 years 1 months ago
Impact of Parallel Workloads on NoC Architecture Design
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar...
RTCSA
2007
IEEE
16 years 23 days ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
DATE
2006
IEEE
154views Hardware» more  DATE 2006»
16 years 17 days ago
An integrated open framework for heterogeneous MPSoC design space exploration
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
Federico Angiolini, Jianjiang Ceng, Rainer Leupers...
CODES
2005
IEEE
16 years 4 days ago
A power estimation methodology for systemC transaction level models
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
Nagu R. Dhanwada, Ing-Chao Lin, Vijay Narayanan