5005 search results - page 754 / 1001 » The Design and Analysis of Parallel Algorithms |
170
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DAC
2000
ACM
16 years 7 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
182
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all ...
128
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ISQED
2010
IEEE
16 years 1 months ago
2010
IEEE
— Algorithms and tools used for IC implementation do not show deterministic and predictable behaviors with input parameter changes. Due to suboptimality and inaccuracy of underly...
167
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LCTRTS
2010
Springer
16 years 1 months ago
2010
Springer
In this paper, we present a novel system modeling language which targets primarily the development of source-level multiprocessor memory aware optimizations. In contrast to previo...
147
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DAC
2009
ACM
16 years 1 months ago
2009
ACM
The latest advancements in the commercial formal model checkers have enabled the integration of formal property verification with the conventional testbench based methods in the o...