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» The Design and Analysis of Parallel Algorithms
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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
16 years 1 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
CVPR
2007
IEEE
16 years 8 months ago
Leveraging temporal, contextual and ordering constraints for recognizing complex activities in video
We present a scalable approach to recognizing and describing complex activities in video sequences. We are interested in long-term, sequential activities that may have several par...
Benjamin Laxton, Jongwoo Lim, David J. Kriegman
HPCA
2009
IEEE
16 years 7 months ago
Variation-aware dynamic voltage/frequency scaling
Fine-grained dynamic voltage/frequency scaling (DVFS) is an important tool in managing the balance between power and performance in chip-multiprocessors. Although manufacturing pr...
Sebastian Herbert, Diana Marculescu
FPGA
2009
ACM
201views FPGA» more  FPGA 2009»
16 years 1 months ago
A high-performance FPGA architecture for restricted boltzmann machines
Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of...
Daniel L. Ly, Paul Chow
CISS
2008
IEEE
16 years 1 months ago
On wireless network scheduling with intersession network coding
Abstract—Cross-layer optimization including congestion control, routing, and scheduling has shown dramatic throughput improvement over layered designs for wireless networks. In p...
Chih-Chun Wang, Ness B. Shroff