5005 search results - page 685 / 1001 » The Design and Analysis of Parallel Algorithms |
194
Voted
DAC
2004
ACM
16 years 7 months ago
2004
ACM
Bounded Model Checking (BMC) relies on solving a sequence of highly correlated Boolean satisfiability (SAT) problems, each of which corresponds to the existence of counter-example...
183
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DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
Despite the growing research effort in formal verification, constraint-based random simulation remains an integral part of design validation, especially for large design componen...
171
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ATS
2000
IEEE
15 years 11 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
164
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DAC
2003
ACM
16 years 7 months ago
2003
ACM
We present practical algorithms for the synthesis of crosstalk cancelling equalizing filters. We examine designs optimized for the traditional l2 metric and introduce an approach ...
190
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DAC
2003
ACM
15 years 12 months ago
2003
ACM
Reduction of an extracted netlist is an important pre-processing step for techniques such as model order reduction in the design and analysis of VLSI circuits. This paper describe...