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» The Design, Implementation, and Evaluation of Jade
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HPCA
2005
IEEE
16 years 10 days ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ACMACE
2005
ACM
16 years 9 days ago
Rendezvous: supporting real-time collaborative mobile gaming in high latency environments
Despite the ever increasing popularity of handheld, networked gaming consoles, fully interactive real-time, multiplayer games designed for these platforms have yet to become a rea...
Angie Chandler, Joe Finney
AOSD
2005
ACM
16 years 9 days ago
Role-based refactoring of crosscutting concerns
Improving the structure of code can help developers work with a software system more efficiently and more consistently. To aid developers in re-structuring the implementation of c...
Jan Hannemann, Gail C. Murphy, Gregor Kiczales
SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
16 years 8 days ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
176
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EGC
2005
Springer
16 years 8 days ago
A Monitoring Architecture for Control Grids
Abstract. Monitoring systems are nowadays ubiquitous in complex environments, such as Grids. Their use is fundamental for performance evaluation, problem spotting, advanced debuggi...
Alexandru Iosup, Nicolae Tapus, Stéphane Vi...