Sciweavers

2763 search results - page 153 / 553
» The Dangerous 'All' in Specifications
Sort
View
EURODAC
1994
IEEE
105views VHDL» more  EURODAC 1994»
15 years 10 months ago
On Design Rule Correct Maze Routing
This paper addresses the problem of design rule correct routing, i.e. the avoidance of illegal wiring patterns during routing. These illegal wiring patterns are due to the set of ...
Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen...
CHI
1993
ACM
15 years 10 months ago
ADEPT: Advanced Design Environment for Prototyping with Task Models
tasks to be performed. This Abstract Artifact Model is a description of the form of the artifact(s) without any nt to concrete implementation detail. The Abstract Artifact Model is...
Peter Johnson, Stephanie Wilson, Panos Markopoulos...
DAC
1994
ACM
15 years 10 months ago
Incorporating Speculative Execution in Exact Control-Dependent Scheduling
- This paper describes a symbolic formulation that allows incorporation of speculative operation execution (preexecution) in an exact control-dependent scheduling of arbitrary forw...
Ivan P. Radivojevic, Forrest Brewer
SPAA
1992
ACM
15 years 10 months ago
Subset Barrier Synchronization on a Private-Memory Parallel System
A global barrier synchronizes all processors in a parallel system. This paper investigates algorithms that allow disjoint subsets of processors to synchronize independently and in...
Anja Feldmann, Thomas R. Gross, David R. O'Hallaro...
IFIP
1989
Springer
15 years 10 months ago
Broadcasting with Selective Reduction
ÐBSR (Broadcasting with Selective Reduction) is a PRAM more powerful than any CRCW PRAM. In order to extend the Broadcast Instruction of BSR and make it more useful for a large cl...
Selim G. Akl, G. R. Guenther