In the geometric data model [6], spatio-temporal data are modelled as a finite collection of triangles that are transformed by time-dependent affinities. To facilitate querying an...
Due to skewed scaling of interconnect delay and cell delay with technology scaling, modern VLSI timing closure requires use of extensive buffer insertion. Inserting a large number...
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pa...
A key step in the design of cyclo-static real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure, which means that tasks...
Instances of the Boolean satisfiability problem (SAT) arise in many areas of circuit design and verification. These instances are typically constructed from some human-designed ar...
Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah...
SAT (Boolean satisfiability) has become the primary Boolean reasoning engine for many EDA applications, so the efficiency of SAT solving is of great practical importance. Recently...