We examine the design space of auction mechanisms and identify three core activities that structure this space. Formal parameters qualifying the performance core activities enable...
Peter R. Wurman, Michael P. Wellman, William E. Wa...
The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper pr...
An analytical performance model for out of order issue superscalar micro-processors is presented. This model quantifies the performance impacts of micro-architecture design option...
: There have been several recent examples of user interface techniques in which the user uses a computational device by physically manipulating the device. This paper proposes that...
Kenneth P. Fishkin, Thomas P. Moran, Beverly L. Ha...
—Design optimization methodologies for AMS-SoCs with analog, digital, and mixed-signal portions have not received significant attention, due to their high complexity. In mixed-s...
Oleg Garitselov, Saraju P. Mohanty, Elias Kougiano...