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FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
15 years 12 months ago
Reducing pin and area overhead in fault-tolerant FPGA-based designs
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...
IV
2002
IEEE
109views Visualization» more  IV 2002»
15 years 11 months ago
Designing Dynamic Interactive Visualisations to Support Collaboration and Cognition
Dynamic interactive visualisations (DIVs) are intended to help coordination and collaboration, through augmenting existing forms of synchronous communication (i.e. phones, face to...
Yvonne Rogers, Harry Brignull, Michael Scaife
CODES
1999
IEEE
15 years 11 months ago
A flexible code generation framework for the design of application specific programmable processors
This paper introduces a flexible code generation framework dedicated to the design of application specific programmable processors. This tool allows the user to build specific com...
François Charot, Vincent Messé
CODES
1999
IEEE
15 years 11 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
ICPP
1999
IEEE
15 years 11 months ago
Adaptive Bubble Router: A Design to Improve Performance in Torus Networks
A router design for torus networks that significantly reduces message latency over traditional wormhole routers is presented in this paper. This new router implements virtual cut-...
Valentin Puente, Ramón Beivide, José...