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ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
15 years 10 months ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...
CNSR
2010
IEEE
164views Communications» more  CNSR 2010»
15 years 9 months ago
Buffered Crossbar Fabrics Based on Networks on Chip
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin
USENIX
2008
15 years 8 months ago
Large-scale Virtualization in the Emulab Network Testbed
Network emulation is valuable largely because of its ability to study applications running on real hosts and "somewhat real" networks. However, conservatively allocating...
Mike Hibler, Robert Ricci, Leigh Stoller, Jonathon...
ACMACE
2008
ACM
15 years 8 months ago
Mobile exergaming
With many industrialized societies bearing the cost of an increasingly sedentary on the health of their populations there is a need to find new ways of encouraging physical activi...
Carlos Garcia Wylie, Paul Coulton
ALGOSENSORS
2008
Springer
15 years 8 months ago
Simple Robots in Polygonal Environments: A Hierarchy
With the current progress in robot technology and related areas, sophisticated moving and sensing capabilities are at hand to design robots capable of solving seemingly complex tas...
Jan Brunner, Matús Mihalák, Subhash ...