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DATE
2000
IEEE
114views Hardware» more  DATE 2000»
15 years 11 months ago
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths
Designs which do not fully utilize their arithmetic datapath components typically exhibit a significant overhead in power consumption. Whenever a module performs an operation who...
Michael Münch, Norbert Wehn, Bernd Wurth, Ren...
DATE
2000
IEEE
108views Hardware» more  DATE 2000»
15 years 11 months ago
A 50 Mbit/s Iterative Turbo-Decoder
Very low bit error rate has become an important constraint in high performance communication systems that operate at very low signal to noise ratios: due to their impressive codin...
F. Viglione, Guido Masera, Gianluca Piccinini, Mas...
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Voted
ICCAD
2000
IEEE
148views Hardware» more  ICCAD 2000»
15 years 11 months ago
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders
—As the complexity of digital filters is dominated by the number of multiplications, many works have focused on minimizing the complexity of multiplier blocks that compute the co...
Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park
ICPP
2000
IEEE
15 years 11 months ago
Multilayer VLSI Layout for Interconnection Networks
Current VLSI technology allows more than two wiring layers and the number is expected to rise in future. In this paper, we show that, by designing VLSI layouts directly for an L-l...
Chi-Hsiang Yeh, Emmanouel A. Varvarigos, Behrooz P...
IEEEPACT
2000
IEEE
15 years 11 months ago
Address Partitioning in DSM Clusters with Parallel Coherence Controllers
Recent research suggests that DSM clusters can benefit from parallel coherence controllers. Parallel controllers require address partitioning and synchronization to avoid handlin...
Ilanthiraiyan Pragaspathy, Babak Falsafi