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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 8 days ago
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
— This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insen...
Ankur Agiwal, Montek Singh
ICDCS
2005
IEEE
16 years 8 days ago
On Exploring Channel Allocation in the Diverse Data Broadcasting Environment
In recent years, data broadcasting becomes a promising technique to design a mobile information system with power conservation, high scalability and high bandwidth utilization. Ho...
Hao-Ping Hung, Ming-Syan Chen
ICDM
2005
IEEE
168views Data Mining» more  ICDM 2005»
16 years 8 days ago
A Scalable Collaborative Filtering Framework Based on Co-Clustering
Collaborative filtering-based recommender systems, which automatically predict preferred products of a user using known preferences of other users, have become extremely popular ...
Thomas George, Srujana Merugu
ICITA
2005
IEEE
16 years 7 days ago
DREAM: A Practical Product Line Engineering Using Model Driven Architecture
Both product line engineering (PLE) and model driven architecture (MDA) are emerging as effective paradigms for building a family of applications in cost effective way. PLE suppor...
Soo Dong Kim, Hyun Gi Min, Jin Sun Her, Soo Ho Cha...
ICMCS
2005
IEEE
109views Multimedia» more  ICMCS 2005»
16 years 7 days ago
H.264 HDTV Decoder Using Application-Specific Networks-On-Chip
This paper studied an H.264 HDTV decoder on two multiprocessor system-on-chip architectures. Two types of networks-on-chip, the RAW network and the applicationspecific networks-on...
Jiang Xu, Wayne Wolf, Jörg Henkel, Srimat T. ...