This paper presents a new scheduling technique to improve the speed, power, and scalability of a dynamic scheduler. In a high-performance superscalar processor, the instruction sc...
Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
Stefan Bieschewski, Joan-Manuel Parcerisa, Antonio...
Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density...
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...