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ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
15 years 4 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
183
Voted
SBP
2012
Springer
14 years 2 months ago
Creating Interaction Environments: Defining a Two-Sided Market Model of the Development and Dominance of Platforms
Interactions between individuals, both economic and social, are increasingly mediated by technological systems. Such platforms facilitate interactions by controlling and regularizi...
Walter E. Beyeler, Andjelka Kelic, Patrick D. Finl...
SASP
2008
IEEE
162views Hardware» more  SASP 2008»
16 years 1 months ago
Accelerating Compute-Intensive Applications with GPUs and FPGAs
—Accelerators are special purpose processors designed to speed up compute-intensive sections of applications. Two extreme endpoints in the spectrum of possible accelerators are F...
Shuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadr...
PREMI
2007
Springer
16 years 26 days ago
Self Adaptable Recognizer for Document Image Collections
Abstract. This paper presents an architecture that enables the recognizer to learn incrementally and, thereby adapt to document image collections for performance improvement. We ar...
Million Meshesha, C. V. Jawahar
191
Voted
WWW
2008
ACM
16 years 7 months ago
Utility-driven load shedding for xml stream processing
Because of the high volume and unpredictable arrival rate, stream processing systems may not always be able to keep up with the input data streams-- resulting in buffer overflow a...
Mingzhu Wei, Elke A. Rundensteiner, Murali Mani