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» The Cost of Design
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MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
16 years 1 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...
ASAP
2007
IEEE
107views Hardware» more  ASAP 2007»
16 years 1 months ago
A Hardware-Oriented Method for Evaluating Complex Polynomials
A hardware-oriented method for evaluating complex polynomials by solving iteratively a system of linear equations is proposed. Its implementation uses a digit-serial iterations on...
Milos D. Ercegovac, Jean-Michel Muller
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
16 years 1 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ICPP
2007
IEEE
16 years 1 months ago
Difficulty-aware Hybrid Search in Peer-to-Peer Networks
—By combining an unstructured protocol with a DHT-based global index, hybrid peer-to-peer (P2P) improves search efficiency in terms of query recall and response time. The major c...
Hanhua Chen, Hai Jin, Yunhao Liu, Lionel M. Ni
IPPS
2007
IEEE
16 years 1 months ago
Model-Driven Performance Analysis Methodology for Distributed Software Systems
Abstract— A key enabler of the recently popularized, assemblycentric development approach for distributed real-time software systems is QoS-enabled middleware, which provides reu...
Swapna S. Gokhale, Paul J. Vandal, Aniruddha S. Go...