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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 11 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
ISCA
2012
IEEE
262views Hardware» more  ISCA 2012»
13 years 9 months ago
Boosting mobile GPU performance with a decoupled access/execute fragment processor
Smartphones represent one of the fastest growing markets, providing significant hardware/software improvements every few months. However, supporting these capabilities reduces the...
Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychron...
CASES
2004
ACM
15 years 10 months ago
Automatic data partitioning for the agere payload plus network processor
With the ever-increasing pervasiveness of the Internet and its stringent performance requirements, network system designers have begun utilizing specialized chips to increase the ...
Steve Carr, Philip H. Sweany
VLSID
2005
IEEE
102views VLSI» more  VLSID 2005»
16 years 7 months ago
Integrated On-Chip Storage Evaluation in ASIP Synthesis
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....
Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar
WCRE
2003
IEEE
16 years 4 days ago
Identification of Software Instabilities
As software evolves, maintenance practices require a process of accommodating changing requirements while minimizing the cost of implementing those changes. Over time, incompatibi...
Jennifer Bevan, E. James Whitehead Jr.