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174
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INFOCOM
1995
IEEE
15 years 10 months ago
1995
IEEE
Message-based process architectures are widely regarded as an effective method for structuring parallel protocol processing on shared memory multi-processor platforms. A message-b...
206
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ARC
2010
Springer
15 years 10 months ago
2010
Springer
Coarse Grained Reconfigurable Array (CGRA) architectures give high throughput and data reuse for regular algorithms while providing flexibility to execute multiple algorithms on th...
195
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ERSA
2004
15 years 8 months ago
2004
This paper introduces VTsim, a device simulator for Xilinx Virtex-II FPGAs. VTsim is currently a globally synchronous event-driven device simulator modeled at the CLB level. Throu...
204
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WSC
1998
15 years 8 months ago
1998
The Time Warp protocol is considered to be an effective synchronization mechanism for parallel discrete event simulation (PDES). However, it is widely recognized that it suffers o...
153
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IJCAI
1989
15 years 8 months ago
1989
Most implementations of AND-parallelism tackle the shared variable problem by running literals in parallel only if they have no variables in common and thus are independent from e...