Sciweavers

15840 search results - page 577 / 3168
» The Control of Synchronous Systems
Sort
View
ICCAD
1999
IEEE
97views Hardware» more  ICCAD 1999»
15 years 11 months ago
A methodology for correct-by-construction latency insensitive design
In Deep Sub-Micron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the de...
Luca P. Carloni, Kenneth L. McMillan, Alexander Sa...
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
15 years 11 months ago
A Performance Comparison of Contemporary DRAM Architectures
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor ...
COMSWARE
2006
IEEE
15 years 10 months ago
M2MC: Middleware for many to many communication over broadcast networks
M2MC is a new distributed computing middleware designed to support collaborative applications running on devices connected by broadcast networks. Examples of such networks are wire...
Chaitanya Krishna Bhavanasi, Sridhar Iyer
ICPP
1995
IEEE
15 years 10 months ago
Impact of Load Imbalance on the Design of Software Barriers
Software barriers have been designed and evaluated for barrier synchronization in large-scale shared-memory multiprocessors, under the assumption that all processorsreach the sync...
Alexandre E. Eichenberger, Santosh G. Abraham
AINA
2010
IEEE
15 years 10 months ago
Mnesic Evocation: An Isochron-Based Analysis
—Mnesic evocation occurs under the action of a stimulus. A successful evocation is observed as the overrun of a certain threshold of the neuronal activity followed by a medical i...
Hedi Ben Amor, Jacques Demongeot, Nicolas Glade