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CODES
2003
IEEE
15 years 12 months ago
Virtual synchronization technique with OS modeling for fast and time-accurate cosimulation
Hardware/Software cosimulation is the key process to shorten the design turn around time. We have proposed a novel technique, called virtual synchronization, for fast and time acc...
Youngmin Yi, Dohyung Kim, Soonhoi Ha
DATE
2003
IEEE
132views Hardware» more  DATE 2003»
15 years 12 months ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
DATE
2003
IEEE
131views Hardware» more  DATE 2003»
15 years 12 months ago
High Speed and Highly Testable Parallel Two-Rail Code Checker
In this article we propose a high speed and highly testable parallel two-rail code checker, which features a compact structure and is Totally-Self-Checking or Strongly Code-Disjoi...
Martin Omaña, Daniele Rossi, Cecilia Metra
DSD
2003
IEEE
121views Hardware» more  DSD 2003»
15 years 12 months ago
CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors
With shrinking feature size of silicon fabrication technology, architects are putting more and more logic into a single die. While one might opt to use these transistors for build...
Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemi...
DSN
2003
IEEE
15 years 12 months ago
TCP Server Fault Tolerance Using Connection Migration to a Backup Server
This paper describes the design, implementation, and performance evaluation of ST-TCP (Server fault-Tolerant TCP), which is an extension of TCP to tolerate TCP server failures. Th...
Manish Marwah, Shivakant Mishra, Christof Fetzer
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