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ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 9 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
CSE
2009
IEEE
15 years 9 months ago
A Comparative Study of Blocking Storage Methods for Sparse Matrices on Multicore Architectures
Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architectur...
Vasileios Karakasis, Georgios I. Goumas, Nectarios...
SIMUTOOLS
2008
15 years 7 months ago
An 802.16 model for NS2 simulator with an integrated QoS architecture
The IEEE 802.16 technology is emerging as a promising solution for BWA due to its ability to support multimedia services and to operate in multiple physical environments. Also, wi...
Ikbal Chammakhi Msadaa, Fethi Filali, Farouk Kamou...
PDPTA
2000
15 years 7 months ago
Evaluating Multi user Distributed Action Games Architectures on a Corba Platform
The development of distributed applications is rapidly growing and some applications, like those which manipulate graphics, images and sounds, need special care. In this paper, we ...
Hendrik T. Macedo, Alessandro C. M. de Araú...
COMCOM
2004
102views more  COMCOM 2004»
15 years 6 months ago
A scalable architecture for end-to-end QoS provisioning
The Differentiated Services (DiffServ) architecture has been proposed by the Internet Engineering Task Force as a scalable solution for providing end-to-end Quality of Service (Qo...
Spiridon Bakiras, Victor O. K. Li