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VLSID
2010
IEEE
202views VLSI» more  VLSID 2010»
15 years 4 months ago
Processor Architecture Design Using 3D Integration Technology
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, is one of the promising solutions to mitigate the interconnect...
Yuan Xie
ACSC
2007
IEEE
16 years 12 days ago
Architecture of a Web Accelerator For Wireless Networks
With the continuous growth of mobile users and web-based wireless applications, the performance of accessing web services via wireless is becoming one of the key issues. Regular T...
Jian Song, Yanchun Zhang
FCCM
2005
IEEE
89views VLSI» more  FCCM 2005»
15 years 11 months ago
A General Purpose, Highly Efficient Communication Controller Architecture for Hardware Acceleration Platforms
Although researchers have presented individual techniques to efficiently utilize the Peripheral Component Interconnect (PCI) bus, their contributions fail to provide a direct path...
Petersen F. Curt, James P. Durbano, Fernando E. Or...
SBACPAD
2005
IEEE
177views Hardware» more  SBACPAD 2005»
15 years 11 months ago
Automatic Data-Flow Graph Generation of MPI Programs
The Data-Flow Graph (DFG) of a parallel application is frequently used to take scheduling decisions, based on the information that it models (dependencies among the tasks and volu...
Rafael Ennes Silva, Guilherme P. Pezzi, Nicolas Ma...
ICCCN
2007
IEEE
15 years 10 months ago
Implementation of a Wireless Mesh Network Testbed for Traffic Control
Wireless mesh networks (WMN) have attracted considerable interest in recent years as a convenient, flexible and low-cost alternative to wired communication infrastructures in many ...
Kun-Chan Lan, Zhe Wang, Rodney Berriman, Tim Moors...