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VLSISP
2011
241views Database» more  VLSISP 2011»
15 years 29 days ago
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Abstract Fractional Motion Estimation (FME) in highdefinition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various...
Gustavo A. Ruiz, Juan A. Michell
DATE
1998
IEEE
108views Hardware» more  DATE 1998»
15 years 10 months ago
Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor
The demands in terms of processing performance, communication bandwidth and real-time throughput of many multimedia applications are much higher than today's processing archi...
Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin...
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
16 years 1 days ago
FPGA-based architecture for real-time IP video and image compression
–Three-dimensional imaging applications require high resolution images that finally result in high data volumes. Due to bandwidth and storage restrictions, an efficient and robus...
Dimitris Maroulis, Nikos Sgouros, Dionisis Chaikal...
IPPS
2003
IEEE
15 years 11 months ago
Performance Modeling of the Grace Hash Join on Cluster Architectures
Aim of the paper is to develop a concise but comprehensive analytical model for the well-known Grace Hash Join algorithm on cost effective cluster architectures. This approach is ...
Erich Schikuta
DATE
2002
IEEE
114views Hardware» more  DATE 2002»
15 years 11 months ago
A Video Compression Case Study on a Reconfigurable VLIW Architecture
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
Davide Rizzo, Osvaldo Colavin