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CODES
2004
IEEE
15 years 10 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
DAC
2008
ACM
16 years 7 months ago
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
Aydin O. Balkan, Gang Qu, Uzi Vishkin
DAC
2003
ACM
16 years 7 months ago
A complexity effective communication model for behavioral modeling of signal processing applications
In this paper, we argue that the address space of memory regions that participate in inter task communication is over-specified by the traditional communication models used in beh...
M. N. V. Satya Kiran, M. N. Jayram, Pradeep Rao, S...
DAC
2006
ACM
16 years 7 months ago
Power-centric design of high-speed I/Os
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojan...
VLDB
2005
ACM
132views Database» more  VLDB 2005»
16 years 6 months ago
Hash-based labeling techniques for storage scaling
Scalable storage architectures allow for the addition or removal of storage devices to increase storage capacity and bandwidth or retire older devices. Assuming random placement of...
Shu-Yuen Didi Yao, Cyrus Shahabi, Per-Åke Larson