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VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
16 years 6 months ago
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
Koushik Maharatna, Alfonso Troya, Milos Krstic, Ec...
HPCA
2005
IEEE
16 years 6 months ago
A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks
In this paper, we propose a new congestion management strategy for lossless multistage interconnection networks that scales as network size and/or link bandwidth increase. Instead...
Finbar Naven, Ian Johnson, José Duato, Jose...
SEUS
2009
IEEE
16 years 1 months ago
Towards Time-Predictable Data Caches for Chip-Multiprocessors
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
Martin Schoeberl, Wolfgang Puffitsch, Benedikt Hub...
OTM
2009
Springer
16 years 26 days ago
Parallel Interconnection of Broadcast Systems with Multiple FIFO Channels
This paper proposes new protocols for the interconnection of FIFO- and causal-ordered broadcast systems, thus increasing their scalability. They use several interconnection links b...
Rubén de Juan-Marín, Vicent Cholvi, ...
DDECS
2008
IEEE
137views Hardware» more  DDECS 2008»
16 years 24 days ago
Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
Zhonghai Lu, Lei Xia, Axel Jantsch