Sciweavers

1524 search results - page 130 / 305
» The Bandwidth Exchange Architecture
Sort
View
ISCA
2003
IEEE
114views Hardware» more  ISCA 2003»
15 years 11 months ago
Building Quantum Wires: The Long and the Short of It
As quantum computing moves closer to reality the need for basic architectural studies becomes more pressing. Quantum wires, which transport quantum data, will be a fundamental com...
Mark Oskin, Frederic T. Chong, Isaac L. Chuang, Jo...
ISCA
2003
IEEE
212views Hardware» more  ISCA 2003»
15 years 11 months ago
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels
Trends in microprocessors of increasing die size and clock speed and decreasing feature sizes have fueled rapidly increasing performance. However, the limited improvements in DRAM...
Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi...
EUROPAR
2006
Springer
15 years 10 months ago
Optimization of Dense Matrix Multiplication on IBM Cyclops-64: Challenges and Experiences
Abstract. This paper presents a study of performance optimization of dense matrix multiplication on IBM Cyclops-64(C64) chip architecture. Although much has been published on how t...
Ziang Hu, Juan del Cuvillo, Weirong Zhu, Guang R. ...
JTRES
2010
ACM
15 years 6 months ago
WCET driven design space exploration of an object cache
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
Benedikt Huber, Wolfgang Puffitsch, Martin Schoebe...
ASAP
2007
IEEE
136views Hardware» more  ASAP 2007»
16 years 22 days ago
0/1 Knapsack on Hardware: A Complete Solution
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
K. Nibbelink, S. Rajopadhye, R. McConnell