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TJS
2008
95views more  TJS 2008»
15 years 6 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen
TON
1998
80views more  TON 1998»
15 years 6 months ago
Blocking and nonblocking multirate Clos switching networks
— This paper investigates in detail the blocking and nonblocking behavior of multirate Clos switching networks at the connection/virtual connection level. The results are applica...
Soung C. Liew, Ming-Hung Ng, Cathy W. Chan
TMC
2010
119views more  TMC 2010»
15 years 4 months ago
SSUM: Smart Server Update Mechanism for Maintaining Cache Consistency in Mobile Environments
—This paper proposes a cache consistency scheme based on a previously proposed architecture for caching database data in MANETs. The original scheme for data caching stores the q...
Khaleel W. Mershad, Hassan Artail
ERSA
2010
199views Hardware» more  ERSA 2010»
15 years 4 months ago
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
Russell Tessier, Salma Mirza, J. Blair Perot
DCOSS
2005
Springer
15 years 12 months ago
Design of Adaptive Overlays for Multi-scale Communication in Sensor Networks
In wireless sensor networks, energy and communication bandwidth are precious resources. Traditionally, layering has been used as a design principle for network stacks; hence routin...
Santashil PalChaudhuri, Rajnish Kumar, Richard G. ...