Sciweavers

1524 search results - page 127 / 305
» The Bandwidth Exchange Architecture
Sort
View
SIES
2008
IEEE
16 years 20 days ago
Performance evaluation of a java chip-multiprocessor
—Chip multiprocessing design is an emerging trend for embedded systems. In this paper, we introduce a Java multiprocessor system-on-chip called JopCMP. It is a symmetric shared-m...
Christof Pitter, Martin Schoeberl
DCOSS
2007
Springer
16 years 14 days ago
Optimal Cluster Association in Two-Tiered Wireless Sensor Networks
Abstract. In this paper, we study the two-tiered wireless sensor network (WSN) architecture and propose the optimal cluster association algorithm for it to maximize the overall net...
Weizhao Wang, Wen-Zhan Song, Xiang-Yang Li, Kousha...
HOTI
2005
IEEE
15 years 12 months ago
Design of Randomized Multichannel Packet Storage for High Performance Routers
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
Sailesh Kumar, Patrick Crowley, Jonathan S. Turner
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
15 years 11 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
ICDCS
2002
IEEE
15 years 11 months ago
Accelerating Internet Streaming Media Delivery using Network-Aware Partial Caching
Internet streaming applications are affected by adverse network conditions such as high packet loss rates and long delays. This paper aims at mitigating such effects by leveraging...
Shudong Jin, Azer Bestavros, Arun Iyengar