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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
16 years 9 days ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
HICSS
2005
IEEE
136views Biometrics» more  HICSS 2005»
16 years 9 days ago
EA Planning, Development and Management Process for Agile Enterprise Development
In this study, we suggest an enterprise architecture (EA) development process model suitable for EA projects limited in scope and time. Several EA process models have been put for...
Mirja Pulkkinen, Ari P. Hirvonen
ICEIS
2005
IEEE
16 years 9 days ago
Benchmarking an XML Mediator
: In the recent years, XML has become the universal interchange format. Many investigations have been made on storing, querying and integrating XML with existing applications. Many...
Florin Dragan, Georges Gardarin
ICPP
2005
IEEE
16 years 8 days ago
Design and Implementation of a Parallel Performance Data Management Framework
Empirical performance evaluation of parallel systems and applications can generate significant amounts of performance data and analysis results from multiple experiments as perfo...
Kevin A. Huck, Allen D. Malony, Robert Bell, Alan ...
IEEECIT
2005
IEEE
16 years 8 days ago
A Performance and Power Co-optimization Approach for Modern Processors
In embedded systems, performance and power are important inter-related issues that cannot be decoupled. Expensive and extensive simulations in a processor design space are usually...
Yongxin Zhu, Weng-Fai Wong, Cheng-Kok Koh
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