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DAC
1996
ACM
15 years 10 months ago
Integrating Formal Verification Methods with A Conventional Project Design Flow
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...
Ásgeir Th. Eiríksson
ICS
2004
Tsinghua U.
16 years 17 hour ago
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Ravi R. Iyer
KBSE
2008
IEEE
16 years 1 months ago
Architecting for evolvability by means of traceability and features
The frequent changes during the development and usage of large software systems often lead to a loss of architectural quality which hampers the implementation of further changes a...
Robert Brcina, Matthias Riebisch
LCPC
2004
Springer
16 years 6 hour ago
Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
Patrick Carribault, Christophe Lemuet, Jean-Thomas...
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
16 years 8 days ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane