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227
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DATE
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper presents the SPIN micro-network that is a generic, scalable interconnect architecture for system on chip. The SPIN architecture relies on packet switching and point-to-...
164
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GLOBECOM
2006
IEEE
16 years 17 days ago
2006
IEEE
— Implementing a multi-tone (MT) architecture for high-speed backplane electrical links is difficult given the tight power and complexity constraints in this application. This pa...
195
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BPM
2007
Springer
15 years 10 months ago
2007
Springer
Breadth and depth complexity are key challenges in achieving business process fusion as the enabler for value configuration design. The PARM framework is proposed as the requiremen...
186
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CF
2006
ACM
16 years 15 days ago
2006
ACM
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
176
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SAC
2006
ACM
16 years 14 days ago
2006
ACM
In this paper, we describe the design and implementation of a tuple-based distributed memory realized with the use of RFID technology. The key idea – rooted in a more general sc...