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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 8 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
SIGMOD
1996
ACM
132views Database» more  SIGMOD 1996»
15 years 10 months ago
Cost-Based Optimization for Magic: Algebra and Implementation
Magic sets rewriting is a well-known optimization heuristic for complex decision-support queries. There can be many variants of this rewriting even for a single query, which diffe...
Praveen Seshadri, Joseph M. Hellerstein, Hamid Pir...
EDOC
2007
IEEE
16 years 25 days ago
An Enterprise Architecture Alignment Measure for Telecom Service Development
The increasing complexity of modern Information Services (IS) makes necessary to carry on review activities. For many companies, these reviews take place within the framework of t...
Jacques Simonin, Yves Le Traon, Jean-Marc Jé...
DATE
2003
IEEE
141views Hardware» more  DATE 2003»
15 years 11 months ago
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
This paper presents a on-chip stack based memory organization that effectively reduces the energy dissipation in programmable embedded system architectures. Most embedded systems ...
Mahesh Mamidipaka, Nikil D. Dutt
PPOPP
2010
ACM
16 years 1 months ago
An adaptive performance modeling tool for GPU architectures
This paper presents an analytical model to predict the performance of general-purpose applications on a GPU architecture. The model is designed to provide performance information ...
Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. P...