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VTS
2003
IEEE
119views Hardware» more  VTS 2003»
16 years 26 days ago
A Circuit Level Fault Model for Resistive Opens and Bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...
TSD
2001
Springer
16 years 14 hour ago
Determining User Interface Semantics Using Communicating Agents
The Internet offers remote access to many information systems to users independent of time and location. This paper describes an agent based approach to deal with issues that rise ...
L. Ton, Léon J. M. Rothkrantz
ICCAD
2000
IEEE
72views Hardware» more  ICCAD 2000»
16 years 57 min ago
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation
The Charge Sharing (CS) problem is one of notorious noise problems in domino circuits design and test. In this paper, this problem is thoroughly investigated by considering circui...
Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen...
VTS
2000
IEEE
108views Hardware» more  VTS 2000»
15 years 12 months ago
High-Level Observability for Effective High-Level ATPG
This paper focuses on observability, one of the open issues in High-Level test generation. Three different approximate metrics for taking observability into account during RT-leve...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
GLVLSI
1999
IEEE
92views VLSI» more  GLVLSI 1999»
15 years 12 months ago
Fault Coverage Estimation for Early Stage of VLSI Design
This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with ...
Von-Kyoung Kim, Tom Chen, Mick Tegethoff