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EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
15 years 11 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng
FMICS
2006
Springer
15 years 10 months ago
SAT-Based Verification of LTL Formulas
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...
Wenhui Zhang
ACL
2006
15 years 8 months ago
An Effective Two-Stage Model for Exploiting Non-Local Dependencies in Named Entity Recognition
This paper shows that a simple two-stage approach to handle non-local dependencies in Named Entity Recognition (NER) can outperform existing approaches that handle non-local depen...
Vijay Krishnan, Christopher D. Manning
AMC
2007
92views more  AMC 2007»
15 years 7 months ago
An integrated framework for continuous assessment and improvement of manufacturing systems
This paper presents an integrated framework for assessment and ranking of manufacturing systems based on management and organizational performance indicators. The integrated appro...
Ali Azadeh, S. F. Ghaderi, Y. Partovi Miran, V. Eb...
BMCBI
2010
176views more  BMCBI 2010»
15 years 7 months ago
Reverse engineering gene regulatory network from microarray data using linear time-variant model
nd: Gene regulatory network is an abstract mapping of gene regulations in living cells that can help to predict the system behavior of living organisms. Such prediction capability...
Mitra Kabir, Nasimul Noman, Hitoshi Iba