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ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
16 years 15 days ago
Language-Based High Level Transaction Extraction on On-chip Buses
Abstract— With the increasing in silicon densities, SoC designs are the stream in modern electronics systems. Accordingly, the verification for SoC designs is crucial. One of th...
Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chie...
WABI
2005
Springer
107views Bioinformatics» more  WABI 2005»
15 years 12 months ago
Linear Time Algorithm for Parsing RNA Secondary Structure
Abstract Baharak Rastegari and Anne Condon Department of Computer Science, University of British Columbia Abstract. Accurate prediction of pseudoknotted RNA secondary structure is ...
Baharak Rastegari, Anne Condon
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
15 years 10 months ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl
COMCOM
2000
130views more  COMCOM 2000»
15 years 6 months ago
Use Case Maps and LOTOS for the prototyping and validation of a mobile group call system
ABSTRACT -- SPEC-VALUE, a rigorous scenario-driven approach for the description and validation of complex system functionalities at the early stages of design, is presented. It is ...
Daniel Amyot, Luigi Logrippo
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
16 years 6 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski