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» Testing Semantics: Connecting Processes and Process Logics
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MODELS
2009
Springer
16 years 23 days ago
Catch Me If You Can - Debugging Support for Model Transformations
Abstract. Model-Driven Engineering places models as first-class artifacts throughout the software lifecycle requiring the availability of proper transformation languages. Although...
Johannes Schönböck, Gerti Kappel, Angeli...
FDL
2004
IEEE
15 years 10 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
AINA
2007
IEEE
16 years 18 days ago
Fuzzy Logic-Based Event Notification in Sparse MANETs
In the Ad-Hoc InfoWare project, we develop a delay tolerant event notification service for sparse Mobile Ad-Hoc Networks for emergency and rescue operations. In most event notific...
Anna K. Lekova, Katrine Stemland Skjelsvik, Thomas...
DFT
1999
IEEE
114views VLSI» more  DFT 1999»
15 years 10 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
ICA
2010
Springer
15 years 4 months ago
Time Series Causality Inference Using Echo State Networks
One potential strength of recurrent neural networks (RNNs) is their – theoretical – ability to find a connection between cause and consequence in time series in an constraint-...
Norbert Michael Mayer, Oliver Obst, Chang Yu-Chen