6704 search results - page 174 / 1341 » Testing Scenario-Based Models |
150
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TC
1998
15 years 6 months ago
1998
—Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q << k, a process termed space compaction. The ...
176
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ICCAD
2008
IEEE
16 years 3 months ago
2008
IEEE
Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
174
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—Multiple-voltage is an effective dynamic power reduction design technique. Recent research has shown that testing for resistive bridging faults in such designs requires ...
152
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ATS
2003
IEEE
15 years 11 months ago
2003
IEEE
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
185
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DAC
1999
ACM
15 years 10 months ago
1999
ACM
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...