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ITC
2003
IEEE
167views Hardware» more  ITC 2003»
15 years 11 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
DELTA
2002
IEEE
15 years 11 months ago
Address and Data Scrambling: Causes and Impact on Memory Tests
: The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a lar...
A. J. van de Goor, Ivo Schanstra
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
15 years 11 months ago
Parametric Fault Simulation and Test Vector Generation
Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This...
Khaled Saab, Naim Ben Hamida, Bozena Kaminska
COMPSAC
1999
IEEE
15 years 10 months ago
Optimal Software Release Policy Based on Cost and Reliability with Testing Efficiency
In this paper, we study the optimal software release problem considering cost, reliability and testing eficiency. We first propose a generalized logistic testing-effort function t...
Chin-Yu Huang, Sy-Yen Kuo, Michael R. Lyu
MA
2010
Springer
86views Communications» more  MA 2010»
15 years 4 months ago
Tests for multiple regression based on simplicial depth
A general approach for developing distribution free tests for general linear models based on simplicial depth is applied to multiple regression. The tests are based on the asympto...
Robin Wellmann, Christine H. Müller