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ICCAD
1998
IEEE
96views Hardware» more  ICCAD 1998»
15 years 10 months ago
Test set compaction algorithms for combinational circuits
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
Ilker Hamzaoglu, Janak H. Patel
ATS
1997
IEEE
88views Hardware» more  ATS 1997»
15 years 10 months ago
On the Adders with Minimum Tests
This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at fault models. In the first part, we prese...
Seiji Kajihara, Tsutomu Sasao
APSEC
2004
IEEE
15 years 10 months ago
An Approach to Detecting Domain Errors Using Formal Specification-Based Testing
Domain testing, a technique for testing software or portions of software dominated by numerical processing, is intended to detect domain errors that usually arise from incorrect i...
Yuting Chen, Shaoying Liu
DATE
2004
IEEE
174views Hardware» more  DATE 2004»
15 years 10 months ago
Graph-Based Functional Test Program Generation for Pipelined Processors
Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has prop...
Prabhat Mishra, Nikil Dutt
WSE
2003
IEEE
15 years 11 months ago
Considering Browser Interaction in Web Application Testing
As web applications evolves, their structure may become more and more complex. Thus, systematic approaches/methods for web application testing are needed. Existing methods take in...
Giuseppe A. Di Lucca, Massimiliano Di Penta