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ETS
2006
IEEE
93views Hardware» more  ETS 2006»
16 years 14 days ago
Retention-Aware Test Scheduling for BISTed Embedded SRAMs
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
Qiang Xu, Baosheng Wang, F. Y. Young
ISSTA
2006
ACM
16 years 11 days ago
Subdomain testing of units and systems with state
This paper extends basic software-testing theory to software components and adds explicit state to the theory. The resulting theory e enough to abstractly model the construction o...
Dick Hamlet
ATS
2003
IEEE
105views Hardware» more  ATS 2003»
15 years 11 months ago
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. R...
ICSE
1997
IEEE-ACM
15 years 10 months ago
Choosing a Testing Method to Deliver Reliability
Testing methods are compared in a model where program failures are detected and the software changed to eliminate them. The question considered is whether it is better to use test...
Phyllis G. Frankl, Richard G. Hamlet, Bev Littlewo...
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
15 years 10 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...