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DFT
2009
IEEE
189views VLSI» more  DFT 2009»
16 years 1 months ago
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Pre-fabrication design verification and post-fabrication chip testing are two important stages in the product realization process. These two stages consume a large part of resourc...
Meng Zhang, Anita Lungu, Daniel J. Sorin
VL
2005
IEEE
119views Visual Languages» more  VL 2005»
16 years 7 days ago
How Well Do Professional Developers Test with Code Coverage Visualizations? An Empirical Study
Despite years of availability of testing tools, professional software developers still seem to need better support to determine the effectiveness of their tests. Without improveme...
Joseph Lawrance, Steven Clarke, Margaret M. Burnet...
ICOIN
2001
Springer
15 years 11 months ago
A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMs
According to the progress of high-speed networks, many communication protocols are specified as concurrent systems. Such systems can be modeled as concurrent deterministic FSMs (D...
Atsushi Fukada, Akio Nakata, Junji Kitamichi, Teru...
COMPSAC
2010
IEEE
15 years 4 months ago
Minimising the Preparation Cost of Runtime Testing Based on Testability Metrics
Abstract--Test cost minimisation approaches have traditionally been devoted to minimising "execution costs", while maximising coverage or reliability. However, in a runti...
Alberto González-Sanchez, Éric Piel,...
CSFW
2011
IEEE
14 years 6 months ago
A Statistical Test for Information Leaks Using Continuous Mutual Information
—We present a statistical test for detecting information leaks in systems with continuous outputs. We use continuous mutual information to detect the information leakage from tri...
Tom Chothia, Apratim Guha