IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Abstract. This paper presents a unified approach to test case generation and conformance test execution in a distributed setting. A model in the object-oriented, concurrent modelin...
Bernhard K. Aichernig, Andreas Griesmayer, Einar B...
This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimati...
I. O'Connor, B. Courtois, K. Chakrabarty, N. Delor...
Together with the concept of reversibility, another relevant physical notion is time-symmetry, which expresses that there is no way of distinguishing between backward and forward t...