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CSREAESA
2010
15 years 4 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
ICSM
2008
IEEE
16 years 1 months ago
Automated severity assessment of software defect reports
In mission critical systems, such as those developed by NASA, it is very important that the test engineers properly recognize the severity of each issue they identify during testi...
Tim Menzies, Andrian Marcus
DFT
1999
IEEE
131views VLSI» more  DFT 1999»
15 years 11 months ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...
ICMCS
2005
IEEE
103views Multimedia» more  ICMCS 2005»
16 years 7 days ago
A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs
Traditional design and test of complex multimedia systems involves a large number of test vectors and is a difficult and time-consuming task. The simulation times are prohibitivel...
Paul R. Schumacher, Marco Mattavelli, Adrian Chiri...
RTSS
1995
IEEE
15 years 10 months ago
Dual Priority Scheduling
In this paper, we present a new strategy for providing flexibility in hard real-time systems. This approach, based on dual priorities, retains the offline guarantees afforded to...
Robert I. Davis, Andy J. Wellings