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» Test set compaction algorithms for combinational circuits
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VLSID
1998
IEEE
116views VLSI» more  VLSID 1998»
15 years 10 months ago
Synthesis of Testable RTL Designs
With several commercial tools becoming available, the high-level synthesis of applicationspeci c integrated circuits is nding wide spread acceptance in VLSI industry today. Existi...
C. P. Ravikumar, Sumit Gupta, Akshay Jajoo
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
15 years 9 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
ICCS
2003
Springer
15 years 11 months ago
Counting Polyominoes: A Parallel Implementation for Cluster Computing
The exact enumeration of most interesting combinatorial problems has exponential computational complexity. The finite-lattice method reduces this complexity for most two-dimension...
Iwan Jensen
AI
2010
Springer
15 years 6 months ago
Implementing logical connectives in constraint programming
Combining constraints using logical connectives such as disjunction is ubiquitous in constraint programming, because it adds considerable expressive power to a constraint language...
Christopher Jefferson, Neil C. A. Moore, Peter Nig...
IJCNN
2007
IEEE
16 years 7 days ago
Default ARTMAP 2
—Default ARTMAP combines winner-take-all category node activation during training, distributed activation during testing, and a set of default parameter values that define a read...
Gregory P. Amis, Gail A. Carpenter