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» Test set compaction algorithms for combinational circuits
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VLSID
1996
IEEE
132views VLSI» more  VLSID 1996»
15 years 10 months ago
A study of composition schemes for mixed apply/compose based construction of ROBDDs
Reduced Ordered Binary Decision Diagrams ROBDDs have traditionally been built in a bottom-up fashion. In this scheme, the intermediate peak memory utilization is often larger than...
Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masah...
ITC
2002
IEEE
86views Hardware» more  ITC 2002»
15 years 11 months ago
Incremental Diagnosis of Multiple Open-Interconnects
With increasing chip interconnect distances, openinterconnect is becoming an important defect. The main challenge with open-interconnects stems from its non-deterministic real-lif...
Jiang Brandon Liu, Andreas G. Veneris, Hiroshi Tak...
DAC
2008
ACM
16 years 7 months ago
DeFer: deferred decision making enabled fixed-outline floorplanner
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
Jackey Z. Yan, Chris Chu
GLVLSI
2005
IEEE
99views VLSI» more  GLVLSI 2005»
15 years 11 months ago
An empirical study of crosstalk in VDSM technologies
We perform a detailed study of various crosstalk scenarios in VDSM technologies by using a distributed model of the crosstalk site and make a number of key observations about the ...
Shahin Nazarian, Massoud Pedram, Emre Tuncer
IJPRAI
2002
93views more  IJPRAI 2002»
15 years 5 months ago
Improving Stability of Decision Trees
Decision-tree algorithms are known to be unstable: small variations in the training set can result in different trees and different predictions for the same validation examples. B...
Mark Last, Oded Maimon, Einat Minkov