624 search results - page 35 / 125 » Test set compaction algorithms for combinational circuits |
186
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ITC
1993
IEEE
15 years 10 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
142
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ICRA
2010
IEEE
15 years 4 months ago
2010
IEEE
We present an efficient algorithm for solving the ray-shooting problem on high dimensional sets. Our algorithm computes the intersection of the boundary of a compact convex set w...
151
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TCAD
1998
15 years 5 months ago
1998
—New methods for fault-effect propagation and state justification that use finite-state-machine sequences are proposed for sequential circuit test generation. Distinguishing se...
150
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DATE
2007
IEEE
16 years 9 days ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
172
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TCSV
2002
15 years 5 months ago
2002
Compressed video bitstreams require protection from channel errors in a wireless channel. The threedimensional (3-D) SPIHT coder has proved its efficiency and its real-time capabi...