624 search results - page 16 / 125 » Test set compaction algorithms for combinational circuits |
126
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ICCAD
2005
IEEE
16 years 2 months ago
2005
IEEE
The presence of unknown values in the simulation result is a key barrier to effective output response compaction in practice. This paper proposes a simple circuit module, called a...
142
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ATS
2002
IEEE
15 years 11 months ago
2002
IEEE
We propose a methodology that examines design modules and identifies appropriate vector justification and response propagation requirements for hierarchical test. Based on a cel...
168
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CAI
2004
Springer
15 years 5 months ago
2004
Springer
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
148
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ITC
1999
IEEE
15 years 10 months ago
1999
IEEE
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
164
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TVLSI
2008
15 years 5 months ago
2008
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...