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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
16 years 13 days ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
CASES
2003
ACM
16 years 4 days ago
Extending STI for demanding hard-real-time systems
Software thread integration (STI) is a compilation technique which enables the efficient use of an application’s fine-grain idle time on generic processors without special hardw...
Benjamin J. Welch, Shobhit O. Kanaujia, Adarsh See...
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 10 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
DICTA
2008
15 years 8 months ago
Image Reconstruction from Contrast Information
An iterative algorithm for the reconstruction of natural images given only their contrast map is presented. The solution is neuro-physiologically inspired, where the retinal cells...
Asim A. Khwaja, Roland Goecke
AIPS
2006
15 years 8 months ago
Combining Knowledge Compilation and Search for Conformant Probabilistic Planning
We present a new algorithm for conformant probabilistic planning, which for a given horizon produces a plan that maximizes the probability of success under quantified uncertainty ...
Jinbo Huang